W3E16M72SR-XBX - 16Mx72 Registered DDR SDRAM

Datasheet Summary

Description

The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS, dynamic random-access, memory using 5 chips containing 268,435,456 bits.

Each chip is internally conﬁgured as a quad-bank DRAM.

Each of the chip’s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16 bits.

Features

Registered for enhanced performance of bus speeds of 200, 225, and 250 MHz Package:.
219 Plastic Ball Grid Array (PBGA), 32 x 25mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i. e. , source-synchronous data.

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Datasheet Details

Part number	W3E16M72SR-XBX
Manufacturer	White Electronic
File Size	770.06 KB
Description	16Mx72 Registered DDR SDRAM
Datasheet	W3E16M72SR-XBX Datasheet
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White Electronic Designs 16Mx72 Registered DDR SDRAM FEATURES Registered for enhanced performance of bus speeds of 200, 225, and 250 MHz Package: • 219 Plastic Ball Grid Array (PBGA), 32 x 25mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i.e.

Published: Jun 8, 2007 |