W3E16M72SR-XBX - 16Mx72 Registered DDR SDRAM

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Datasheet Details

The 128MByte (1Gb) DDR.

Registered for enhanced performance of bus speeds of 200, 225, and 250 MHz Package:.
219 Plastic Ball Grid Array (PBGA), 32 x 25mm 2.5V ±0.2V core power supply 2.5V I/O (SSTL_2 compatible) Differential clock inputs (CK and CK#) Commands entered on each positive CK edge Internal pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Programmable Burst length: 2,4 or 8 Bidirectional data strobe (DQS) transmitted/ received with data, i. e. , source-synchronous data.

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