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White Electronic Designs
WED2DG472512V-D2
ADVANCED*
16MB (4x512Kx72) SYNC BURST-PIPELINE, DUAL KEY DIMM
FEATURES
4x512Kx72 Synchronous, Synchronous Burst Pipeline Architecture; Single Cycle Deselect Linear and Sequential Burst Support via MODE pin Clock Controlled Registered Module Enable (EM#) Clock Controlled Registered Bank Enables (E1#, E2#, E3#, E4#) Clock Controlled Byte Write Mode Enable (BWE#) Clock Controlled Byte Write Enables (BW1# - BW8#) Clock Controlled Registered Address Clock Controlled Registered Global Write (GW#) Asynchronous Output Enable (G#) Internally Self-Timed Write Individual Bank Sleep Mode Enables (ZZ1, ZZ2, ZZ3, ZZ4) Gold Lead Finish 3.3V ± 10% Operation Frequency(s): 200, 166, 150, and 133MHz Access Speed(s): tKHQV = 3.0, 3.5, 3.