WED2DL32512V Overview
The WEDC SyncBurst - SRAM family employs high-speed, lowpower CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 16Mb SyncBurst SRAMs integrate two 512K x 16 SRAMs into a single BGA package to provide 512K x 32 configuration. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK).
WED2DL32512V Key Features
- 119-bump BGA package s Low capacitive bus loading
- SRAM family employs high-speed, lowpower CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 16Mb Sy
- This data sheet describes a product under development, not fully characterized, and is subject to change without notice