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WED2ZL64512S - Synchronous Pipeline NBL SRAM

Description

The WEDC SyncBurst - SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process.

WEDC’s 32Mb Sync SRAM integrate two 512K x 32 SRAMs into a single BGA package to provide 512K x 64 configuration.

Features

  • Fast clock speed: 166, 150, 133, and 100MHz.
  • Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns.
  • Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns.
  • Seperate +2.5V ± 5% power supplys for core I/O (VCC + VCCQ).
  • Double Word Write Control.
  • Clock-controlled and registered addresses, data I/Os and control signals.
  • Packaging:.
  • 119 bump BGA package.
  • Low capacitive bus loading WED2ZL64512S.

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Datasheet Details

Part number WED2ZL64512S
Manufacturer White Electronic
File Size 496.87 KB
Description Synchronous Pipeline NBL SRAM
Datasheet download datasheet WED2ZL64512S Datasheet

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www.DataSheet4U.com White Electronic Designs 512K x 64 Synchronous Pipeline NBL SRAM FEATURES  Fast clock speed: 166, 150, 133, and 100MHz  Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns  Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns  Seperate +2.5V ± 5% power supplys for core I/O (VCC + VCCQ)  Double Word Write Control  Clock-controlled and registered addresses, data I/Os and control signals  Packaging: • 119 bump BGA package  Low capacitive bus loading WED2ZL64512S DESCRIPTION The WEDC SyncBurst - SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 32Mb Sync SRAM integrate two 512K x 32 SRAMs into a single BGA package to provide 512K x 64 configuration.
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