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CDC2509B Datasheet 3.3-v Phase-lock-loop Clock Driver

Manufacturer: Texas Instruments

Overview: CDC2509B 3.3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS613C − SEPTEMBER 1998 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for this Device D Designed to Meet PC SDRAM Registered DIMM Specification D Spread Spectrum Clock Compatible D Operating Frequency 25 MHz to 125 MHz D Phase Error Time Minus Jitter at 66 MHz to 100 MHz Is ±150 ps D Jitter (peak − peak) at 66 MHz to 100 MHz Is ±80 ps D Jitter (cycle − cycle) at 66 MHz to 100 MHz Is |100 ps| D Available in Plastic 24-Pin TSSOP D Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications D Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs D Separate Output Enable for Each Output Bank D External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input D On-Chip Series Damping Resistors D No External RC Network Required D Operates at 3.

General Description

The CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock drivers.

They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

They are specifically designed for use with synchronous DRAMs.

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