CDC2582 Datasheet | Texas Instruments

D Low Output Skew for Clock-Distribution and Clock-Generation Applications D Operates at 3.3-V VCC D Distributes Differential LVPECL Clock Inputs to 12 TTL-patible Outputs D Two Select Inputs Configure Up to Nine Outputs to Operate at One-Half or Double the Input Frequency D No External RC Network Required D External Feedback Input (FBIN) Is Used to Synchronize the Outputs With the Clock Inputs CDC2582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS SCAS379B - FEBRUARY 1993 - REVISED FEBRUARY 1996 D Application for Synchronous DRAMs D Outputs Have Internal 26-Ω Series Resistors to Dampen Transmission-Line Effects D State-of-the-Art EPIC-ΙΙB™ BiCMOS...