Datasheet Summary
D Low Output Skew, Low Pulse Skew for
Clock-Distribution and Clock-Generation
Applications
D TTL-patible Inputs and
CMOS-patible Outputs
D Distributes One Clock Input to Eight
Outputs
- Four Same-Frequency Outputs
- Four Half-Frequency Outputs
D Distributed VCC and Ground Pins Reduce
Switching Noise
D High-Drive Outputs (- 48-mA IOH,
48-mA IOL)
D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design
Significantly Reduces Power Dissipation
D Package Options Include Plastic
Small-Outline (DW)
CDC337 CLOCK DRIVER WITH 3-STATE OUTPUTS
SCAS330B
- DECEMBER 1990
- REVISED OCTOBER 1998
DW PACKAGE (TOP VIEW)
Y3 1 GND 2
Y4 3 VCC 4
OE 5 CLR 6 VCC 7
Q4 8 GND 9
Q3 10
20 Y2 19 GND 18 Y1 17 VCC 16 CLK 15 GND...