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CDCDLP223 Datasheet Preview

CDCDLP223 Datasheet

3.3V Clock Synthesizer

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3.3 V Clock Synthesizer for DLP™ Systems
CDCDLP223
SCAS836 – DECEMBER 2006
FEATURES
High-Performance Clock Synthesizer
Uses a 20 MHz Crystal Input to Generate
Multiple Output Frequencies
Integrated Load Capacitance for 20 MHz
Oscillator Reducing System Cost
All PLL Loop Filter Components are
Integrated
Generates the Following Clocks:
– REF CLK 20 MHz (Buffered)
– XCG CLK 100 MHz With SSC
– DMD CLK 200-400 MHz With Selectable
SSC
Very Low Period Jitter Characteristic:
±100 ps at 20 MHz Output
±75 ps at 100 MHz and 200–400 MHz
Outputs
Includes Spread-Spectrum Clocking (SSC),
With Down Spread for 100 MHz and Center
Spread for 200–400 MHz
HCLK Differential Outputs for the 100 MHz
and the 200–400 MHz Clock
Operates From Single 3.3-V Supply
Packaged in TSSOP20
Characterized for the Industrial Temperature
Range -40°C to 85°C
ESD Protection Exceeds JESD22
2000-V Human-Body Model (A114-C) –
MIL-STD-883, Method 3015
TYPICAL APPLICATIONS
Central Clock Generator for DLP™ Systems
DESCRIPTION
The CDCDLP223 is a PLL-based high performance
clock synthesizer that is optimized for use in DLP™
systems. It uses a 20 MHz crystal to generate the
fundamental frequency and derives the frequencies
for the 100 MHz HCLK and the 300 MHz HCLK
output. Further, the CDCDLP223 generates a
buffered copy of the 20 MHz Crystal Oscillator
Frequency at the 20 MHz output terminal.
CDCDLP223 PIN ASSIGNMENTS
XIN
XOUT
VSS
VDD
20MHZ
VSS
EN
IDO
SDATA
SCLK
1 TSSOP 20 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
IREF
VDD
100MHZ
100MHZ
VSS
VSS
300MHZ
300MHZ
VSS
VDD
The 100 MHz HCLK output provides the reference
clock for the XDR Clock Generator (CDCD5704).
Spread-spectrum clocking with 0.5% down spread,
which reduces Electro Magnetic Interference (EMI),
is applied in the default configuration. The
spread-spectrum clocking (SSC) is turned on and off
via the serial control interface.
The 300 MHz HCLK output provides a 200-400 MHz
clock signal for the DMD Control Logic of the DLP™
Control ASIC. Frequency selection in 20 MHz steps
is possible via the serial control interface.
Spread-spectrum clocking with ±1.0% or ±1.5%
center spread is applied, which can be disabled via
the serial control interface
The CDCDLP223 features a fail safe start-up circuit,
which enables the PLLs only if a sufficient supply
voltage is applied and a stable oscillation is delivered
from the crystal oscillator. After the crystal start-up
time and the PLL stabilization time, all outputs are
ready for use.
The CDCDLP223 works from a single 3.3-V supply
and is characterized for operation from –40°C to
85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated




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CDCDLP223 Datasheet Preview

CDCDLP223 Datasheet

3.3V Clock Synthesizer

No Preview Available !

CDCDLP223
SCAS836 – DECEMBER 2006
FUNCTIONAL BLOCK DIAGRAM
XOUT
XIN
Crystal
Oscillator
20 Mhz
www.ti.com
LVTTL
20 Mhz
SSC PLL 1
OUT = 100 Mhz
–0.5% SSC
HCLK out
100 Mhz
VDD
150 KW
EN
SCLK
SDATA
2-Wire Serial
Interface
Control
Logic
IDO
SSC PLL 2
OUT = 200-400 Mhz
±1.0% and
±1.5% SSC
VDD
150 KW
VDD
VSS
HCLK out
300 Mhz
IREF
TERMINAL
XIN
XOUT
SDATA
SCLK
20 MHz
100 MHz
100 MHz
300 MHz
300 MHz
VDD
VSS
IREF
EN
IDO
TERMINAL FUNCTIONS
PIN
1
2
9
10
5
18
17
14
13
4,11,19
3,6,12,15,16
20
7
8
TYPE
DESCRIPTION
I Crystal oscillator input for 20-MHz crystal in parallel resonance
O Crystal oscillator output for 20-MHz crystal in parallel resonance
I/O Open drain Data I/O, 2-wire serial interface controller, internal 1-Mpullup
I Interface Clock Clock input, 2-wire serial interface controller, internal 1-Mpullup
O LVTTL Clock output, 20 MHz (buffered output from crystal oscillator)
O HCLK Clock output for XDR clock generator
O HCLK Clock output for XDR clock generator
O HCLK Clock output for DMD system
O HCLK Clock output for DMD system
Power
3.3 V Power supply
Ground
Ground
O RREF to GND IREF pin for HCLK output drive-current biasing
I LVTTL
Output enable, 20 MHz, 100 MHz and 200–400 MHz outputs, 150 kpullup, default =
logic high
I LVTTL
Sets 2-wire serial interface ID address bit A0, 150 kpull-up resistor, default = logic
high
Table 1. EN Pin (20 MHz, 100 MHz and 300 MHz Clocks)
EN PIN
1
0
DESCRIPTION
All HCLK outputs, and 20-MHz outputs enabled, detailed device configurations are determined by 2-wire serial interface
settings.
All HCLK = true Hi-Z, both PLLs are powered down and 20-MHz output in Hi-Z and Crystal Oscillator disabled, EN overrides
2-wire serial interface settings.
2 Submit Documentation Feedback


Part Number CDCDLP223
Description 3.3V Clock Synthesizer
Maker etcTI
Total Page 8 Pages
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