CDCDLP223 Overview
The CDCDLP223 is a PLL-based high performance clock synthesizer that is optimized for use in DLP™ systems. It uses a 20 MHz crystal to generate the fundamental frequency and derives the frequencies for the 100 MHz HCLK and the 300 MHz HCLK output. Further, the CDCDLP223 generates a buffered copy of the 20 MHz Crystal Oscillator Frequency at the 20 MHz output terminal. CDCDLP223 PIN ASSIGNMENTS XIN XOUT The 300 MHz HCLK output provides a 200-400 MHz clock signal for the DMD Control Logic of the DLP™ Control ASIC. Frequency selection in 20 MHz steps is possible via the serial control interface. Spread-spectrum clocking with ±1.0% or ±1.5% center spread is applied, which can be disabled via the serial control interface
CDCDLP223 Key Features
- High-Performance Clock Synthesizer
- Uses a 20 MHz Crystal Input to Generate
- Integrated Load Capacitance for 20 MHz Oscillator Reducing System Cost
- All PLL Loop Filter ponents are Integrated
- Generates the Following Clocks
- REF CLK 20 MHz (Buffered)
- XCG CLK 100 MHz With SSC
- DMD CLK 200-400 MHz With Selectable SSC
- Very Low Period Jitter Characteristic
- ±100 ps at 20 MHz Output
CDCDLP223 Applications
- Central Clock Generator for DLP™ Systems