CDCDB2000 Description
The CDCDB2000 is a 20-output LP-HCSL, DB2000QL pliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-5, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. The SMBus, SBI, and 8 output enable pins allow the configuration and control of all 20 outputs individually. The CDCDB2000 is a DB2000QL derivative buffer and meets or exceeds the system parameters in the DB2000QL specification.
CDCDB2000 Key Features
- 1 20 LP-HCSL outputs with integrated 85-Ω output terminations
- 8 hardware output enable (OE#) controls
- Additive phase jitter after DB2000QL filter
- Supports PCIe Gen 4 and Gen 5 mon Clock
- Spread spectrum-patible
- Cycle-to-cycle jitter: < 50 ps
- Output-to-output skew: < 50 ps
- Input-to-output delay: < 3 ns
- 3.3-V core and IO supply voltages
- Hardware-controlled low power mode (PD#)