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SCAS897A
- JULY 2010
- REVISED OCTOBER 2016
CDCLVD1213 1:4 Low Additive Jitter LVDS Buffer With Divider
1 Features
- 1 1:4 Differential Buffer
- Low Additive Jitter: < 300-fs RMS in 10-kHz to 20-
MHz
- Low Output Skew of 20 ps (Maximum)
- Selectable Divider Ratio 1, /2, /4
- Universal Input Accepts LVDS, LVPECL, and
- 4 LVDS Outputs, ANSI EIA/TIA-644A Standard patible
- Clock Frequency: Up to 800 MHz
- Device Power Supply: 2.375 V to 2.625 V
- Industrial Temperature Range:
- 40°C to 85°C
- Packaged in 3 mm × 3 mm, 16-Pin VQFN (RGT)
- ESD Protection Exceeds 3-kV HBM, 1-kV CDM
3...