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CDCLVD1204 - 2:4 Low Additive Jitter LVDS Buffer

General Description

The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution.

The CDCLVD1204 can accept two clock sources into an input multiplexer.

Key Features

  • 1 2:4 Differential Buffer.
  • Low Additive Jitter:.

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CDCLVD1204 SCAS898B – MAY 2010 – REVISED OCTOBER 2016 CDCLVD1204 2:4 Low Additive Jitter LVDS Buffer 1 Features •1 2:4 Differential Buffer • Low Additive Jitter: <300 fs RMS in 10-kHz to 20-MHz • Low Output Skew of 20 ps (Maximum) • Universal Inputs Accept LVDS, LVPECL, and LVCMOS • Selectable Clock Inputs Through Control Pin • 4 LVDS Outputs, ANSI EAI/TIA-644A Standard Compatible • Clock Frequency: Up to 800 MHz • Device Power Supply: 2.375 V to 2.