CDCLVD1204 Overview
The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The CDCLVD1204 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.
CDCLVD1204 Key Features
- 1 2:4 Differential Buffer
- Low Output Skew of 20 ps (Maximum)
- Universal Inputs Accept LVDS, LVPECL, and
- Selectable Clock Inputs Through Control Pin
- 4 LVDS Outputs, ANSI EAI/TIA-644A Standard
- Clock Frequency: Up to 800 MHz
- Device Power Supply: 2.375 V to 2.625 V
- Industrial Temperature Range: -40°C to 85°C
- Packaged in 3 mm × 3 mm, 16-Pin VQFN (RGT)
- ESD Protection Exceeds 3 kV HBM, 1 kV CDM