Datasheet Summary
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SCAS903A
- JUNE 2010
- REVISED AUGUST 2010
Dual 1:4 Low Additive Jitter LVDS Buffer
Check for Samples: CDCLVD2104
Features
- Dual 1:4 Differential Buffer
- Low Additive Jitter <300 fs, RMS in
10 kHz to 20 MHz
- Low Within Bank Output Skew of 35ps (Max)
- Universal Inputs Accept LVDS, LVPECL,
LVCMOS
- One Input Dedicated for Four Output Buffers
- 8 LVDS Outputs, ANSI EIA/TIA-644A Standard patible
- Clock Frequency up to 800 MHz
- 2.375- 2.625V Device Power Supply
- LVDS Reference Voltage, VAC_REF, Available for
Capacitive Coupled Inputs
- Industrial Temperature Range
- 40°C to 85°C
- Packaged in 5mm × 5mm 28-Pin QFN (RHD)
- ESD Protection Exceeds 3 kV HBM, 1 kV...