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SCAS887B
- SEPTEMBER 2009
- REVISED JANUARY 2016
CDCLVP2106 12-LVPECL Output, High-Performance Clock Buffer
1 Features
- 1 Dual 1:6 Differential Buffer
- Two Clock Inputs
- Universal Inputs Can Accept LVPECL, LVDS,
LVCMOS/LVTTL
- 12 LVPECL Outputs
- Maximum Clock Frequency: 2 GHz
- Maximum Core Current Consumption: 92 mA
- Very Low Additive Jitter: <100 fs, RMS in 10-kHz to 20-MHz Offset Range
- 2.375-V to 3.6-V Device Power Supply
- Maximum Propagation Delay: 550 ps
- Maximum Within Bank Output Skew: 20 ps
- LVPECL Reference Voltage, VAC_REF, Available for Capacitive-Coupled Inputs
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