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CDCLVP2102 - High-Performance Clock Buffer

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General Description

The CDCLVP2102 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications.

It has a maximum clock frequency up to 2 GHz.

Each buffer block consists of one input that feeds two LVPECL outputs.

Overview

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CDCLVP2102 SCAS881C – AUGUST 2009 – REVISED JANUARY 2016 CDCLVP2102 Four-LVPECL Output, High-Performance Clock Buffer.

Key Features

  • 1 Dual 1:2 Differential Buffer.
  • Two Clock Inputs.
  • Universal Inputs Can Accept LVPECL, LVDS, LVCMOS/LVTTL.
  • Four LVPECL Outputs.
  • Maximum Clock Frequency: 2 GHz.
  • Maximum Core Current Consumption: 48 mA.
  • Very Low Additive Jitter:.

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