CDCLVP2106 Description
The CDCLVP2106 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from two LVPECL, LVDS, or LVCMOS inputs for a variety of munication applications. It has a maximum clock frequency up to 2 GHz. Each buffer block consists of one input that feeds two LVPECL outputs.
CDCLVP2106 Key Features
- 1 Dual 1:6 Differential Buffer
- Two Clock Inputs
- Universal Inputs Can Accept LVPECL, LVDS
- 12 LVPECL Outputs
- Maximum Clock Frequency: 2 GHz
- Maximum Core Current Consumption: 92 mA
- Very Low Additive Jitter: <100 fs, RMS in 10-kHz
- 2.375-V to 3.6-V Device Power Supply
- Maximum Propagation Delay: 550 ps
- Maximum Within Bank Output Skew: 20 ps