* 1
* Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1
* Spread Spectrum Clock Compatible
* Operating Frequency 20 MHz to 175 MHz
* Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps
* Jitter (cyc - cyc) at 60 MHz to 17
CDCVF2509A Datasheet (403.57 KB)
CDCVF2509A
403.57 KB
3.3-v phase-lock loop clock driver.
CDCVF2509A www.ti.com SCAS765E APRIL 2004 REVISED FEBRUARY 2010 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE Check fo.
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