Datasheet4U Logo Datasheet4U.com

DS92LV3222 - Link-II Serializer/Deserializer

Download the DS92LV3222 datasheet PDF. This datasheet also covers the DS92LV3221 variant, as both devices belong to the same link-ii serializer/deserializer family and are provided as variant models within a single manufacturer datasheet.

Description

The DS92LV3221 (SER) serializes a 32-bit data bus into 2 embedded clock LVDS serial channels for a data payload rate up to 1.6 Gbps over cables such as CATx, or backplanes FR-4 traces.

Features

  • 1.
  • 2 Wide Operating Range Embedded Clock SER/DES.
  • Up to 32-bit Parallel LVCMOS Data.
  • 20 to 50 MHz Parallel Clock.
  • Up to 1.6 Gbps.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DS92LV3221-etcTI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
DS92LV3222 20-50 MHz 32-Bit Channel Link II Serializer/Deserializer National Semiconductor Corporation
DS92LV3221 20-50 MHz 32-Bit Channel Link II Serializer/Deserializer National Semiconductor Corporation
DS92LV3241 20-85 MHz 32-Bit Channel Link II Serializer/Deserializer National Semiconductor Corporation
DS92LV3242 20-85 MHz 32-Bit Channel Link II Serializer/Deserializer National Semiconductor Corporation
DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver National Semiconductor

Other Datasheets by Texas Instruments

Part Number Description
DS92LV3221 Link-II Serializer/Deserializer
DS92LV3241 Link-II Serializer/Deserializer
DS92LV3242 Link-II Serializer/Deserializer
DS92LV010A Bus LVDS 3.3/5.0V Single Transceiver
DS92LV040A 4-Channel Bus LVDS Transceiver

Full PDF Text Transcription

Click to expand full text
DS92LV3221, DS92LV3222 www.ti.com SNLS319C – OCTOBER 2009 – REVISED APRIL 2013 DS92LV3221/DS92LV3222 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer Check for Samples: DS92LV3221, DS92LV3222 FEATURES 1 •2 Wide Operating Range Embedded Clock SER/DES – Up to 32-bit Parallel LVCMOS Data – 20 to 50 MHz Parallel Clock – Up to 1.6 Gbps Application Data Paylod • Simplified Clocking Architecture – No Separate Serial Clock Line – No Reference Clock Required – Receiver Locks to Random Data • On-chip Signal Conditioning for Robust Serial Connectivity – Transmit Pre-Emphasis – Data Randomization – DC-Balance Encoding – Receive Channel Deskew – Supports up to 10m CAT-5 at 1.
Published: |