SN65LVDS390 Datasheet | Texas Instruments

Features - 1 Four- ('390), Eight- ('388A), or Sixteen- ('386) Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard - Integrated 110-Ω Line Termination Resistors on LVDT Products - Designed for Signaling Rates Up to 250 Mbps - SN65 Versions Bus-Terminal ESD Exceeds 15 k V - Operates From a Single 3.3-V Supply - Typical Propagation Delay Time of 2.6 ns - Output Skew 100 ps (Typical) Part-To-Part Skew Is Less Than 1 ns - LVTTL Levels Are 5-V Tolerant - Open-Circuit Fail Safe - Flow-Through Pinout - Packaged in Thin Shrink Small-Outline Package With 20-mil Terminal Pitch 2 Applications - Wireless Infrastructure - Tele Infrastructure - Printer 3 Description This family of 4-, 8-, or 16-differential line receivers (with optional integrated termination) implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SN65LVDS386 SN65LVDT386 SN75LVDS386 TSSOP (64) 17.00 mm × 6.10 mm SN75LVDT386 SN65LVDS388A SN65LVDT388A SN75LVDS388A TSSOP (38) 9.70 mm × 4.40 mm SN75LVDT388A SOIC (16) TSSOP (16) 9.90 mm × 3.91 mm 5.00 mm × 4.40 mm SN65LVDT390 SOIC (16) TSSOP (16) 9.90 mm × 3.91 mm 5.00 mm × 4.40...