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SN74SSQEA32882 - 28-Bit to 56-Bit Registered Buffer

Description

This JEDEC SSTE32882-compliant, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 registered DIMMs with VDD of 1.5 V and on DDR3L registered DIMMs with VDD of 1.35 V.

All inputs are 1.5 V and 1.35 V CMOS compatible.

Features

  • 1.
  • JEDEC SSTE32882 Compliant.
  • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs.
  • CKE Powerdown Mode for Optimized System Power Consumption.
  • 1.5V/1.35V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and CK) and Distributing to Four Differential Outputs.
  • 1.5V/1.35V CMOS Inputs.
  • Checks Parity on Command and Address (CS-Gated) Data Inputs.
  • Configurable Driver Strength.

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Full PDF Text Transcription

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SN74SSQEA32882 www.ti.com SCAS879B – JUNE 2009 – REVISED OCTOBER 2010 28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clock PLL Driver Check for Samples: SN74SSQEA32882 FEATURES 1 • JEDEC SSTE32882 Compliant • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs • CKE Powerdown Mode for Optimized System Power Consumption • 1.5V/1.35V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and CK) and Distributing to Four Differential Outputs • 1.5V/1.
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