SN74SSQEA32882 datasheet, buffer equivalent, Texas Instruments

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Features and benefits

1
* JEDEC SSTE32882 Compliant
* 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs
* CKE Powerdown Mode for Optimized System Po.

Application

* DDR3 Registered DIMMs up to DDR3-1600
* DDR3L Registered DIMMs up to DDR3L-1333
* Single-, Dual- and Quad-.

Description

This JEDEC SSTE32882-compliant, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 registered DIMMs with VDD of 1.5 V and on DDR3L registered DIMMs with VDD of 1.35 V. All inputs are 1.5 V an.

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