Description
AS4C128M16D3LC-12BIN AS4C128M16D3LC-12BCN Revision History 2Gb AS4C128M16D3LC 96 ball FBGA PACKAGE Revision Details Rev 1.0 Initial Release Date Feb.
Features
* Overview
* JEDEC Standard Compliant
The 2Gb Double-Data-Rate-3L (DDR3L) DRAMs is
* Power supplies: VDD & VDDQ = +1.35V (1.283V ~ 1.45V) double data rate architecture to achieve high-speed
* Backward compatible to VDD & VDDQ = +1.5V ±0.075V
* Operating temperature: - Commercial :
Applications
* Fully synchronous operation
The chip is designed to comply with all key DDR3L