AS4C16M32SC-7TIN Datasheet (Alliance Semiconductor)

AS4C16M32SC-7TIN, 512M SDRAM

Revision History 512M SDRAM 54/86pin TSOP II Package Revision Details Rev 1.0 Preliminary datasheet AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN Date Sep.

2018 Alliance Memory Inc.

511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc.

reserves the right to change products or specification without notice Confidential - 1 of 24 - Rev.1.0 Sep.

2018 AS4C16M32SC-7TIN AS4C32M16SC-7TIN AS4C64M8SC-7TIN 1 Overview This chapter gives an overview of th

AS4C16M32SC-7TIN Features

* Fully Synchronous to Positive Clock Edge

* Fast clock rate: 133 MHz

* Multiple Burst Read with Single Write Operation

* Four Banks controlled by BA0 & BA1

* Data Mask for Byte Control (x16,x32)

* Programmable Mode registers - CAS Latency: 1 or 2 or 3