* Overview
* Fast clock rate: 200 MHz
* Differential Clock CK & CK
* Bi-directional DQS
* DLL enable/disable by EMRS
* Fully synchronous operation
* Internal pipeline architecture
* Four internal banks, 1M x 16-bit for each bank
* Progr
AS4C4M16D1A Datasheet (1.82 MB)
AS4C4M16D1A
Alliance Semiconductor
1.82 MB
Ddr.
4Mx16 DDR1-AS4C4M16D1A
Revision History AS4C4M16D1A - 66-pin TSOPII PACKAGE
Revision Details Rev 1.1 Preliminary datasheet
Date July 2015
Alliance .
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