AS4C4M32S Datasheet - Alliance Semiconductor

AS4C4M32S 4M x 32 bit Synchronous DRAM

Table 1. Pin Details Symbol Type Description CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock Enable: CKE activates (HIGH) and d.

AS4C4M32S Revision History AS4C4M32S- 90 Ball TFBGA PACKAGE Revision Rev 1.0 Rev 2.0 Rev 3.0 Details Preliminary datasheet Added 166MHz option -6 clock cycle time Typing error page 1 change to header of Key Specificatons from AS4C8M32S to AS4C4M32S Typing error Frequency in Ordering information 7-BCN reflected as 133MHz changed to 143MHz Typing error Part no Header on pages 2-45 Corrected from AS4C2M32S to AS4C4M32S Date February 2013 February 2013 May 2014 May 2014 May 2.

AS4C4M32S Features

* Fast access time from clock: 5.4/5.4 ns

* Fast clock rate: 166/143 MHz

* Fully synchronous operation

* Internal pipelined architecture

* Four internal banks (1M x 32-bit x 4bank)

* Programmable Mode - CAS Latency: 2 or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type

AS4C4M32S Datasheet (1.07 MB)