AS4C4M16SA Datasheet - Alliance Semiconductor

AS4C4M16SA - 64M Synchronous DRAM

Table 3. Pin Details Symbol CLK CKE BA0,BA1 Type Input Input Input Description Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock Enable: CKE activates.

AS4C4M16SA-Automotive Revision History Revision Rev 1.0 Rev 2.0 Rev 3.0 Details Preliminary datasheet Add 143MHZ parts. 1. Remove AS4C4M16SA-7BAN, AS4C4M16SA-7TAN parts. 2. Add part number system on the last page. Date March 2014 February 2015 March 2015 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice. Confidential 0 Rev. 3.0 Mar. /2015 AS4C4M16SA.

AS4C4M16SA Features

* Fast access time from clock: 5.4 ns

* Fast clock rate: 166 MHz

* Fully synchronous operation

* AEC-Q100 Compliant

* Internal pipelined architecture

* 1M word x 16-bit x 4-bank

* Programmable Mode registers - CAS Latency: 2 or 3 - Burst Length: 1, 2, 4, 8, or full page -

AS4C4M16SA-AllianceSemiconductor.pdf