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AS4C512M16D3LA - 8Gbit DDR3L SDRAM

AS4C512M16D3LA Description

Revision History 8Gbit DDR3L SDRAM 8 BANKS X 64Mbit X 16 - Dual Die Package (DDP) 96ball FBGA Package Revision Details Rev 1.0 Preliminary datasheet .
Pin CK, CK CKE CS ODT RAS, CAS, WE DM BA0 - BA2 A0 - A15 A10 / AP A12 / BC RESET DQ DQSL, DQSL DQSU, DQSU NC Type Input Input Input Input Input Inpu.

AS4C512M16D3LA Features

* - Double-data-rate architecture; two data transfers per clock cycle - The high-speed data transfer is realized by the 8 bits prefetch pipe- lined architecture - Bi-directional differential data strobe (DQS and DQS) is transmitted/ received with data for capturing data at the receiver - DQS is edge-a

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8Gbit DDR3L SDRAM Alliance Semiconductor
Alliance Semiconductor AS4C512M16D3LA-like datasheet