Description
SYSTEM .
3
ARM Cortex-A55 Processor 5 SHARC Processor 6 SHARC+ Core Architecture 8 System Infrastructure 10 System Memory Map 11 Security Features 14 Se.
Features
* Dual-enhanced SHARC+ high performance floating-point cores Up to 1000 MHz per SHARC+ core 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed
Arm Co
Applications
* SYSTEM CONTROL
SECURITY AND PROTECTION SYSTEM PROTECTION UNIT (SPU)
SYSTEM MEMORY PROTECTION UNIT (SMPU) CRYPTOGRAPHIC HARDWARE
ACCELERATOR FAULT MANAGEMENT UNIT (FMU) ArmĀ® TrustZoneĀ® SECURITY AND
CRYPTOGRAPHIC EXTENSION QUAD CRC (WITH MemDMA) WATCHDOGS OTP MEMORY
THERMAL MONITOR UNIT (TMU)
PROGRAM