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ADSP-TS101S TigerSHARC Embedded Processor

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Description

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GENERAL DESCRIPTION. 2 Dual Compute Blocks.

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Features

* 300 MHz, 3.3 ns Instruction Cycle Rate 6M Bits of Internal
* On-Chip
* SRAM Memory 19 mm ؋ 19 mm (484-Ball) or 27 mm ؋ 27 mm (625-Ball) PBGA Package Dual Computation Blocks
* Each Containing an ALU, a Multiplier, a Shifter, and a Register File Dual Integer ALUs, Providing Data Addr

Applications

* Performs Exceptionally Well on DSP Algorithm and I/O Benchmarks (See Benchmarks in Table 1 and Table 2) Supports Low Overhead DMA Transfers Between Internal Memory, External Memory, Memory-Mapped Peripherals, Link Ports, Host Processors, and Other (Multiprocessor) DSPs Eases DSP Programming Through

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