Description
a PERFORMANCE .
Features
* 6.25 ns Instruction Cycle Time, for up to 160 MIPS Sustained Performance ADSP-218x Family Code Compatible with the Same Easy to Use Algebraic Syntax Single-Cycle Instruction Execution Single-Cycle Context Switch between Two Sets of Comwww. DataSheet4U. com putation and Memory Instructions InstructionApplications
* The ADSP-2191M combines the ADSP-219x family base architecture (three computational units, two data address generators, and a program sequencer) with three serial ports, two SPI-compatible ports, one UART port, a DMA controller, three programmable timers, general-purpose Programmable Flag pins, extADSP2191M Distributors
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