ADSP-21362 - SHARC Processors

Analog Devices

Datasheet Details

3 SHARC Family Core Architecture 4 Family Peripheral Architecture 6 I/O Processor

include: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios Available in 136-ball CSP_BGA and 144-lead LQFP_EP packages SIMD Core Instruction Cache 5 stage Sequencer DAG1/2 Timer PEx PEy FLAGx/IRQx/ TMREXP JTAG Block 0 RAM/ROM Internal Memory Block 1 RAM/ROM Block 2 RAM Block 3 RAM DMD 64-BIT PMD 64-BIT S C.

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Published: Jan 17, 2007 |