CS2501 Datasheet (Cirrus Logic) - Fractional-N Clock Multiplier

CS2501, Fractional-N Clock Multiplier

The CS2501 is a system-clocking device incorporating a programmable phase-locked loop (PLL).

The hybrid analog/ digital PLL architecture comprises a delta-sigma fractional-N analog PLL and a digital frequency-locked loop (FLL).

The CS2501 enables clock generation from a stable timing reference clock

CS2501 Features

* I²C/SPI control port

* Fractional clock multiplier and jitter reduction using hybrid analog/digital PLL

* Generates low-jitter 6

* 75 MHz clock (CLK_OUT), synchronized to a 50 Hz

* 30 MHz low-quality or intermittent frequency reference (CLK_IN)

* Flexi