Datasheet4U Logo Datasheet4U.com

CY29973 3.3V 125-MHz Multi-Output Zero Delay Buffer

📥 Download Datasheet  Datasheet Preview Page 1

Description

CY29973 3.3V 125-MHz Multi-Output Zero Delay Buffer .
44, 46, 48, 50 QA(3:0) 32, 34, 36, 38 QB(3:0) 16, 18, 21, 23 QC(3:0) 29 FB_OUT 25 SYNC VDDC O 42, 43 40, 41 19, 20 5, 26, 27 52 31 6 7 8 2 SELA.

📥 Download Datasheet

Preview of CY29973 PDF
datasheet Preview Page 2 datasheet Preview Page 3

Datasheet Specifications

Part number
CY29973
Manufacturer
Cypress Semiconductor
File Size
272.16 KB
Datasheet
CY29973_CypressSemiconductor.pdf
Description
3.3V 125-MHz Multi-Output Zero Delay Buffer

Features

* Output Frequency up to 125 MHz 12 Clock Outputs: Frequency Configurable 350 ps max. Output to Output Skew Configurable Output Disable Two Reference Clock Inputs for Dynamic Toggling Oscillator or PECL Reference Input
* Spread S

Applications

* the CY29973 offers a low voltage PECL clock input as a PLL reference. This allows the user to use LVPECL as the primary clock distribution device to take advantage of its far superior skew performance. The CY29973 then can lock onto the LVPECL reference and translate with near zero delay to low skew

CY29973 Distributors

📁 Related Datasheet

📌 All Tags

Cypress Semiconductor CY29973-like datasheet