* Separate independent read and write data ports
* Supports concurrent transactions
* 250-MHz clock for high bandwidth
* 2-word burst on all accesses
* Double data rate (DDR) interfaces on both read and write ports at 250 MHz (data transferred at 500 MHz)
* Two input clocks (
CYRS1542AV18 Datasheet (454.44 KB)
CYRS1542AV18
Cypress Semiconductor
454.44 KB
72-mbit qdr ii+ sram two-word burst architecture.
CYRS1542AV18
CYRS1544AV18
72-Mbit QDR® II+ SRAM Two-Word Burst Architecture with RadStop™ Technology
72-Mbit QDR® II+ SRAM Two-Word Burst Architectur.
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