The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst
M12L128168A-7BVAG2N Features
* JEDEC standard 3.3V power supply
* LVTTL compatible with multiplexed address
* Four banks operation
* MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave )
* All inputs are sampled at the p
Datasheet Details
M12L128168A-7BVAG2N, M12L128168A-5TVG2N
ESMT
1.26 MB
Synchronous dram.
This datasheet PDF includes multiple part numbers: M12L128168A-7BVAG2N, M12L128168A-5TVG2N.
Please refer to the document for exact specifications by model.
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