Description
ESMT SDRAM .
The M12L128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits.
Features
* JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clo
Applications
* BALL CONFIGURATION (TOP VIEW)
(BGA90, 8mmX13mmX1mm Body, 0.8mm Ball Pitch)
1
2
3 456
7
8
9
A DQ26 DQ24 VSS
VDD DQ23 DQ21
B DQ28 VDDQ VSSQ
VDDQ VSSQ DQ19
C VSSQ DQ27 DQ25
DQ22 DQ20 VDDQ
D VSSQ DQ29 DQ30
DQ17 DQ18 VDDQ
E VDDQ DQ31 NC
NC DQ16 VSSQ
F VSS DQM3 A3
A2 DQM2 VDD
G A4 A5