M12L128324A-7TG2C, M12L128324A - 1M x 32 Bit x 4 Banks Synchronous DRAM

Datasheet Details

Part number	M12L128324A-7TG2C, M12L128324A
Manufacturer	ESMT
File Size	1.11 MB
Description	1M x 32 Bit x 4 Banks Synchronous DRAM
Datasheet	M12L128324A_EliteSemiconductor.pdf
Note	This datasheet PDF includes multiple part numbers: M12L128324A-7TG2C, M12L128324A. Please refer to the document for exact specifications by model.

The M12L128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits.

JEDEC standard 3.3V power supply.
LVTTL compatible with multiplexed address.
Four banks operation.
MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1, 2, 4, 8 & full page) - Burst Type (Sequential & Interleave).
All inputs are sampled at the positive going edge of the system clock.
DQM for masking.
Auto & self refresh.
64ms refresh period (4K cycle) M12L128324A (2C) 1M x 32 Bit x 4 Banks Synchronous DRAM.

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Published: Mar 24, 2019 |