Description
The device is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 16 bits.
Features
- JEDEC standard 3.3V power supply.
- LVTTL compatible with multiplexed address.
- Four banks operation.
- MRS cycle with address key programs
- CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 & full page ) - Burst Type ( Sequential & Interleave ).
- All inputs are sampled at the positive going edge of the system clock.
- Burst Read single write operation.
- DQM for masking.
- Auto & self refresh.
- 64ms refresh period (8K cycle).
- All Pb-free products are RoHS-.
M12L5121632A-ESMT.pdf
