M12L64322A-5TG2S Datasheet, DRAM, ESMT

M12L64322A-5TG2S Features

• Dram JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1, 2, 4, 8 &

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M12L64322A-5TG2S

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ESMT

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📄 Datasheet

Description:

512k x 32 bit x 4 banks synchronous dram. The M12L64322A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits. Synchronous desi

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M12L64322A-5TG2S

ESMT

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