M13D64322A - Low Power DDR SDRAM

Datasheet Details

JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) No DLL; CLK to DQS is not synchronized. Differential clock inputs (CLK and CLK ) Four bank operation CAS Latency : 2, 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8, 16 & full page Special function support - DS (Drive Strength) - Deep Power Down Mode (DPD Mode) M13D64322A (2S) 512K x 32 Bit x 4 Banks Low Power DDR SDRAM All inputs except data & DM ar.

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Published: Sep 20, 2018 |