M13S5121632A - Double Data Rate SDRAM

ESMT

M13S5121632A Datasheet Preview — Preview of M13S5121632A PDF

Datasheet Details

Part number	M13S5121632A
Manufacturer	ESMT
File Size	1.70 MB
Description	Double Data Rate SDRAM
Datasheet	M13S5121632A-ESMT.pdf

M13S5121632A Product details

Description

Pin Name Function Pin Name Function A0~A12, BA0, BA1 Address inputs - Row address A0~A12 - Column address A0~A9 A10/AP: AUTO Precharge BA0, BA1: Bank selects (4 Banks) DM is an input mask signal for write data.LDM, UDM LDM corresponds to the data on DQ0~DQ7; UDM correspond to the data on DQ8~DQ15. DQ0~DQ15 Data-in/Data-out CLK, CLK Clock input RAS Row address strobe CAS Column address strobe WE Write enable VSS Ground VDD LDQS, UDQS Power Bi-directional Data Strobe.LDQS corr

Features

Double-data-rate architecture, two data transfers per clock cycle.
Bi-directional data strobe (DQS).
Differential clock inputs (CLK and CLK ).
DLL aligns DQ and DQS transition with CLK transition.
Four bank operation.
CAS Latency : 2, 2.5, 3.
Burst Type : Sequential and Interleave.
Burst Length : 2, 4, 8.
All inputs except data & DM are sampled at the rising edge of the system clock (CLK).
Data I/O transitions on both edges of data strobe (DQS).

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Published: Sep 20, 2018 |