M13S5121632A - Double Data Rate SDRAM
Pin Name Function Pin Name Function A0~A12, BA0, BA1 Address inputs - Row address A0~A12 - Column address A0~A9 A10/AP: AUTO Precharge BA0, BA1: Bank selects (4 Banks) DM is an input mask signal for write data.
LDM, UDM LDM corresponds to the data on DQ0~DQ7; UDM correspond to the data on DQ8
M13S5121632A Features
* Double-data-rate architecture, two data transfers per clock cycle
* Bi-directional data strobe (DQS)
* Differential clock inputs (CLK and CLK )
* DLL aligns DQ and DQS transition with CLK transition
* Four bank operation
* CAS Latency : 2, 2.5, 3
* Burst Type : Sequent
