M13S256328A - 2M x 32 Bit x 4 Banks Double Data Rate SDRAM
(M13S256328A) Pin Name Function Address inputs - Row address A0~A11 - Column address A0~A7, A9 A8/AP : AUTO Precharge BA0, BA1 : Bank selects (4 Banks) Data-in/Data-out Row address strobe Column address strobe Write enable Ground Power Bi- directional Data Strobe.
DQS0 correspond to the data on DQ0~
M13S256328A Features
* z z z z z z z z z z z z z z z z z z z z z M13S256328A 2M x 32 Bit x 4 Banks Double Data Rate SDRAM JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ an
