M13S128324A - Double Data Rate SDRAM
Pin Name Function Pin Name Function A0~A11, BA0,BA1 Address inputs - Row address A0~A11 - Column address A0~A7 A8/AP : AUTO Precharge BA0, BA1 : Bank selects (4 Banks) DM0~DM3 DM is an input mask signal for write data.
DM0 corresponds to the data on DQ0~DQ7; DM1 corresponds to the data on DQ
M13S128324A Features
* Double-data-rate architecture, two data transfers per clock cycle
* Bi-directional data strobe (DQS)
* Differential clock inputs (CLK and CLK )
* DLL aligns DQ and DQS transition with CLK transition
* Quad bank operation
* CAS Latency : 2, 2.5, 3
* Burst Type : Sequenti
