M13S128168A Datasheet - Elite Semiconductor Memory Technology

M13S128168A Double Data Rate SDRAM

Pin Name Function Pin Name Function A0~A11, BA0, BA1 Address inputs - Row address A0~A11 - Column address A0~A8 A10/AP: AUTO Precharge BA0, BA1: Bank selects (4 Banks) DM is an input mask signal for write data. LDM, UDM LDM corresponds to the data on DQ0~DQ7; UDM correspond to the data on DQ8~D.

M13S128168A Features

* Double-data-rate architecture, two data transfers per clock cycle

* Bi-directional data strobe (DQS)

* Differential clock inputs (CLK and CLK )

* DLL aligns DQ and DQS transition with CLK transition

* Four bank operation

* CAS Latency : 2, 2.5, 3

* Burst Type : Sequent

M13S128168A_EliteSemiconductorMemoryTechnology.pdf

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Datasheet Details

Part number:

M13S128168A

Manufacturer:

Elite Semiconductor Memory Technology

File Size:

1.76 MB

Description:

double data rate sdram.

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M13S128168A M13S128168A Double Data Rate SDRAM Elite Semiconductor Memory Technology

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