* z z z z z z z z z z z z z z z z z z z z M13S2561616A 4M x 16 Bit x 4 Banks Double Data Rate SDRAM JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe (DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and
M13S2561616A Datasheet (753.94 KB)
M13S2561616A
Elite Semiconductor Memory Technology
753.94 KB
4m x 16 bit x 4 banks double data rate sdram.
www.DataSheet4U.com ESMT Revision History Revision 0.1 (28 Apr. 2006) - Original M13S2561616A Revision 1.0 (07 Jun. 2006) - Delete Preliminary at e.
📁 Related Datasheet
M13S256328A 2M x 32 Bit x 4 Banks Double Data Rate SDRAM (Elite Semiconductor Memory Technology)
M13S128168A Double Data Rate SDRAM (Elite Semiconductor Memory Technology)
M13S128324A Double Data Rate SDRAM (ESMT)
M13S32321A 256K x 32 Bit x 4 Banks Double Data Rate SDRAM (Elite Semiconductor Memory Technology)
M13S5121632A Double Data Rate SDRAM (ESMT)
M13S64164A-4BG2Y 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)
M13S64164A-4TG2Y 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)
M13S64164A-5BG 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)
M13S64164A-5BG2Y 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)
M13S64164A-5TG 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)
TAGS
Image Gallery
