M13S64164A-5TG - 1M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT

Datasheet Details

Part number	M13S64164A-5TG
Manufacturer	ESMT
File Size	1.51 MB
Description	1M x 16 Bit x 4 Banks Double Data Rate SDRAM
Datasheet	M13S64164A-5TG-ESMT.pdf

z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe (DQS) z On-chip DLL z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition z Quad bank operation z CAS Latency : 2, 2.5, 3 z Burst Type : Sequential and Interleave z Burst Length : 2, 4, 8 z All inputs except data & DM are sampled at the rising edge of the system clock(CLK) z Data I/O transitions on both edges of data strobe.

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Published: Mar 25, 2019 |