M13S64164A-6BG Features
* z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe (DQS) z On-chip DLL z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition z Quad bank operation z CAS Latency : 2, 2.5, 3 z Bu
Datasheet Details
M13S64164A-6BG, M13S64164A-5TG
ESMT
1.51 MB
1m x 16 bit x 4 banks double data rate sdram.
This datasheet PDF includes multiple part numbers: M13S64164A-6BG, M13S64164A-5TG.
Please refer to the document for exact specifications by model.
M13S64164A-6BG Distributor
📁 Related Datasheet
M13S64164A-6BG2Y 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)
M13S64164A-6TG 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)
M13S64164A-6TG2Y 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)
M13S64164A-4BG2Y 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)
M13S64164A-4TG2Y 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)
M13S64164A-5BG 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)
M13S64164A-5BG2Y 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)
M13S64164A-5TG 1M x 16 Bit x 4 Banks Double Data Rate SDRAM (ESMT)
