M13S64164A-6BG2Y - 1M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S64164A-6BG2Y Features
* z Double-data-rate architecture, two data transfers per clock cycle z Bi-directional data strobe (DQS) z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition z Four bank operation z CAS Latency : 2, 2.5, 3 z Burst Type : Sequential and Interleave z Burst L
