M13S64164A-6BG2Y Features
* z Double-data-rate architecture, two data transfers per clock cycle z Bi-directional data strobe (DQS) z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition z Four bank operation z CAS Latency : 2, 2.5, 3 z Burst Type : Sequential and Interleave z Burst L
M13S64164A_EliteSemiconductorMemoryTechnology.pdf
Datasheet Details
M13S64164A-6BG2Y, M13S64164A
ESMT
1.19 MB
1m x 16 bit x 4 banks double data rate sdram.
This datasheet PDF includes multiple part numbers: M13S64164A-6BG2Y, M13S64164A.
Please refer to the document for exact specifications by model.
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M13S64164A-6BG2Y Distributor
