M13S64164A-6TG - 1M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S64164A-6TG Features
* z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe (DQS) z On-chip DLL z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition z Quad bank operation z CAS Latency : 2, 2.5, 3 z Bu
