M14F5121632A Datasheet - ESMT

M14F5121632A DDR II SDRAM

Pin Name A0~A12, BA0,BA1 DQ0~DQ15 RAS CAS WE VSS VDD DQS, DQS (LDQS, LDQS UDQS, UDQS) ODT NC Function Address inputs - Row address A0~A12 - Column address A0~A9 A10/AP : Auto Precharge BA0, BA1 : Bank selects (4 Banks) Data-in/Data-out Command input Command input Command input Ground Power Pin Na.

M14F5121632A Features

* JEDEC Standard

* VDD / VDDQ = 1.55V ± 0.075V

* Internal pipelined double-data-rate architecture; two data access per clock cycle

* Bi-directional differential data strobe (DQS, DQS ); DQS can be disabled for single-ended data strobe operation.

* On-chip DLL

* Differential c

M14F5121632A-ESMT.pdf