M15T4G16256A-EFBG2S, M15T4G16256A - DDR3 SDRAM

Datasheet Details

Part number	M15T4G16256A-EFBG2S, M15T4G16256A
Manufacturer	ESMT
File Size	8.07 MB
Description	DDR3 SDRAM
Datasheet	M15T4G16256A-ESMT.pdf
Note	This datasheet PDF includes multiple part numbers: M15T4G16256A-EFBG2S, M15T4G16256A. Please refer to the document for exact specifications by model.

The 4Gb Double-Data-Rate-3 (DDR3(L)) DRAM is double data rate architecture to achieve high-speed operation.

and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a differential DQS pair in a source synchronous fashion. These devices operate with a single 1.35V -0.067V/+0.1V or 1.5V ± 0.075V power supply and are available in BGA packages. DDR3(L) SDRAM Addressing Configuration 256Mb x 16 # of Bank 8 Bank Address BA0.

📁 M15T4G16256A-EFBG2S Similar Datasheet

Other Datasheets by ESMT

Published: Aug 19, 2025 |